M32C80 Datasheet, PDF (311/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
23. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
[ Read Timing ] (1φ +1φ Bus Cycle)
BCLK
CSi
ADi
BHE
RD
DB
td(BCLK-CS)
18ns.max⁽¹⁾
tcyc
td(BCLK-AD)
18ns.max⁽¹⁾
td(BCLK-RD)
18ns.max
tac1(RD-DB)⁽²⁾
tac1(AD-DB)⁽²⁾
Hi-Z
tsu(DB-BCLK)
26ns.min⁽¹⁾
th(BCLK-CS)
-3ns.min
th(RD-CS)
0ns.min
th(BCLK-AD)
-3ns.min
th(RD-AD)
0ns.min
th(BCLK-RD)
-5ns.min
th(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)+1)
tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n=a+b)
[ Write timing ] (1φ +1φ Bus Cycle)
BCLK
CSi
ADi
BHE
WR,WRL,
WRH
td(BCLK-CS)
18ns.max
th(BCLK-CS)
-3ns.min
tcyc
td(BCLK-AD)
18ns.max
th(WR-CS)⁽³⁾
th(BCLK-AD)
-3ns.min
td(BCLK-WR)
18ns.max
tw(WR)⁽³⁾
td(DB-WR)⁽³⁾
th(WR-AD)⁽³⁾
th(BCLK-WR)
-5ns.min
th(WR-DB)⁽³⁾
DBi
Vcc1=Vcc2=5V
NOTE:
3. Varies with operation frequency:
td(DB-WR)=(tcyc x m-20)ns.min
(if external bus cycle is aφ+bφ, m=b)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(if external bus cycle is aφ+bφ , n=(bx2)-1)
Measurement Conditions:
• VCC1=VCC2=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
tcyc= ¹⁰⁹
f(BCLK)
Figure 23.2 VCC1=VCC2=5V Timing Diagram (1)
Rev. 1.00 Nov. 01, 2005 ^{Page 292} of 330
REJ09B0271-0100