M32C80 Datasheet, PDF (345/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
24. Precautions (Programmable I/O Ports)
24.12 Programmable I/O Ports
• Because ports P72 to P75, P80, and P81 have three-phase PWM output forced cutoff function, they are
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affected by the three-phase motor control timer function and the NMI pin when these ports are set for
output functions (port output, timer output, three-phase PWM output, serial I/O output, intelligent I/O
output).
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Table 24.4 shows the INVC0 register setting, the NMI pin input level and the state of output ports.
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Table 24.4 INVC0 Register and the NMI Pin
Setting Value of the INVC0 Register
INV02 Bit
INV03 Bit
Signal level Applied P72 to P75, P80, P81 Pin States
to the NMI Pin (When Setting Them as Output Pins)
0
-
(Not Using the Three-Phase
Motor Control Timer
Functions)
-
Provides functions selected by the
PS1, PSL1, PSC, PS2, PSL2
registers
1
(Using the Three-Phase
Motor Control Timer
Functions)
0
-
(Three-Phase Motor Control
Timer Output Disabled)
1
H
(Three-Phase Motor Control
Timer Output Enabled)⁽¹⁾
High-impedance state
Provides functions selected by the
PS1, PSL1, PSC, PS2, PSL2
registers
L
High-impedance state
(Forcibly Terminated)
NOTE:
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1. The INV03 bit is set to "0" after a low-level ("L") signal is applied to the NMI pin.
• The availability of pull-up resistors is indeterminate until internal power voltage stabilizes, if the RESET
pin is held "L".
• The input threshold voltage varies between programmable I/O ports and peripheral functions. There-
fore, if the level of the voltage applied to a pin shared by both programmable I/O ports and peripheral
functions is not within the recommended operating condition, VIH and VIL (neither "H" nor "L"), the level
may vary depending on the programmable ports and peripheral functions.
Rev. 1.00 Nov. 01, 2005 ^{Page 326} of 330
REJ09B0271-0100