M32C80 Datasheet, PDF (113/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
10.6.4 Interrupt Response Time
Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt
generation and the execution of the first instruction in an interrupt routine. Interrupt response time in-
cludes the period between an interrupt request generation and the completed execution of an instruction
((a) on Figure 10.6) and the period required to perform an interrupt sequence ((b) on Figure 10.6).
Interrupt request is generated Interrupt request is acknowledged
Instruction ^{Interrupt sequence}
(a)
(b)
Instruction in
interrupt routine
Time
Interrupt response time
(a) Period between an interrupt request generation and the completed execution of an instruction.
(b) Period required to perform an interrupt sequence.
Figure 10.6 Interrupt Response Time
Time (a) varies depending on an instruction being executed. The DIV, DIVX and DIVU instructions
require the longest time (a); 42 cycles when an immediate value or register is set as the divisor.
When the divisor is a value in the memory, the following value is added.
• Normal addressing
:2+X
• Index addressing
:3+X
• Indirect addressing
: 5 + X + 2Y
• Indirect index addressing : 6 + X + 2Y
X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores
indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be
doubled.
Table 10.4 lists time (b), shown Figure 10.6.
Rev. 1.00 Nov. 01, 2005 Page 94 of 330
REJ09B0271-0100