M32C80 Datasheet, PDF (62/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
7. Bus
Example 1:
Example 2:
When the microcomputer accesses the external
space j specified by another chip-select signal in the
next cycle after having accessed the external space i,
both address bus and chip-select signal change.
When the microcomputer accesses SFRs or the
internal RAM area in the next cycle after having
accessed an external space, the chip-select signal
changes but the address bus does not.
Access
External
Space i
Access
External
Space j
Access
External
Space
Access
SFRs,
Internal
RAM Area
Data Bus
Data
Data
Address Bus
Chip-Select Signal
CSk
Chip-Select Signal
CSp
Address
i = 0 to 3
k = 0 to 3
j = 0 to 3, excluding i
p= 0 to 3, excluding k
(See Figure 6.3 for i, j and p, k)
Data Bus
Address Bus
Chip-Select Signal
CSk
Data
Address
k = 0 to 3
Example 3:
Example 4:
When the microcomputer accesses the space i
specified by the same chip-select signal in the next
cycle after having accessed the external space i,
the address bus changes but the chip-select signal
does not.
When the microcomputer does not access any
space in the next cycle after having accessed an
external space (no pre-fetch of an instruction is
generated), neither address bus nor chip-select
signal changes.
Access
External
Space i
Access
External
Space i
Access
External _{No Access}
Space
Data Bus
Address Bus
Chip-Select Signal
CSk
Data
Data
Address
Data Bus
Address Bus
Chip-Select Signal
CSk
Data
Address
i = 0 to 3
k = 0 to 3
(See Figure 6.3 for i and k)
k = 0 to 3
NOTE:
1. The above applies to the address bus and chip-select signal in two consecutive cycles.
By combining these examples, a chip-select signal added by two or more cycles may be output.
Figure 7.2 Address Bus and Chip-Select Signal Outputs (Separate Bus)
Rev. 1.00 Nov. 01, 2005 Page 43 of 330
REJ09B0271-0100