M32C80 Datasheet, PDF (221/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
Table 16.21 Pin Settings in Special Mode 2 (1)
Port
P60
P61
P62
P63
P64
P65
P66
P67
Function
______
SS0 input
PS0 Register
PS0_0=0
CLK0 input (slave) PS0_1=0
CLK0 output (master) PS0_1=1
RxD0 input (master) PS0_2=0
STxD0 output (slave) PS0_2=1
TxD0 output (master) PS0_3=1
SRxD0 input (slave) PS0_3=0
______
SS1 input
PS0_4=0
CLK1 input (slave) PS0_5=0
CLK1 output (master) PS0_5=1
RxD1 input (master) PS0_6=0
STxD1 output (slave) PS0_6=1
TxD1 output (master) PS0_7=1
SRxD1 input (slave) PS0_7=0
Setting
PSL0 Register
–
–
–
–
PSL0_2=1
–
–
–
–
–
–
PSL0_6=1
–
–
PD6 Register
PD6_0=0
PD6_1=0
–
PD6_2=0
–
–
PD6_3=0
PD6_4=0
PD6_5=0
–
PD6_6=0
–
–
PD6_7=0
Table 16.22 Pin Settings (2)
Port
Function
Setting
P70(1)
PS1 Register
TxD2 output (master) PS1_0=1
PSL1 Register
PSL1_0=0
PSC Register
PSC_0=0
SRxD2 input (slave) PS1_0=0
–
–
P71(1)
RxD2 input (master) PS1_1=0
–
–
STxD2 output (slave) PS1_1=1
PSL1_1=1
PSC_1=0
P72
CLK2 input (slave) PS1_2=0
–
–
CLK2 output (master) PS1_2=1
______
P73
SS2 input
PS1_3=0
PSL1_2=0
–
PSC_2=0
–
NOTE:
1. P70 and P71 are ports for the N-channel open drain output.
PD7 Register
–
PD7_0=0
PD7_1=0
–
PD7_2=0
–
PD7_3=0
Table 16.23 Pin Settings (3)
Port
Function
Setting
PS3 Register⁽¹⁾ PSL3 Register
PSC3 Register PD9 Register⁽¹⁾
P90
CLK3 input (slave) PS3_0=0
–
–
PD9_0=0
CLK3 output (master) PS3_0=1
–
–
–
P91
RxD3 input (master) PS3_1=0
–
–
PD9_1=0
STxD3 output (slave) PS3_1=1
PSL3_1=1
–
–
P92
TxD3 output (master) PS3_2=1
PSL3_2=0
–
–
SRxD3 input (slave) PS3_2=0
______
P93
SS3 input
PS3_3=0
_______
P94
SS4 input
PS3_4=0
–
–
PSL3_3=0
–
PSL3_4=0
–
PD9_2=0
PD9_3=0
PD9_4=0
P95
CLK4 input (slave) PS3_5=0
PSL3_5=0
–
PD9_5=0
CLK4 output (master) PS3_5=1
–
–
–
P96
TxD4 output (master) PS3_6=1
–
PSC3_6=0
–
SRxD4 input (slave) PS3_6=0
PSL3_6=0
–
PD9_6=0
P97
RxD4 input (master) PS3_7=0
–
–
PD9_7=0
STxD4 output (slave) PS3_7=1
PSL3_7=1
–
–
NOTE:
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enabled). Do
not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to
set the PD9 and PS3 registers.
Rev. 1.00 Nov. 01, 2005 Page 202 of 330
REJ09B0271-0100