M32C80 Datasheet, PDF(264/352 Page) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

M32C80 Datasheet, PDF (264/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

◁

M32C/80 Group

21. Intelligent I/O

ISRxD0 ISCLK0

CCS1 and CCS0

f1 01

f2n 10

f8 11

0

CKDIR

Transmit

Operation

Clock

1

Receive Operation Clock

Communication Unit 0

G0TB Register

(Transmit Buffer Register)

Transmit

Buffer

Transmit

Register

Clock Wait

Control Circuit

SOF

Generation Circuit

Transmit Data

Generation Circuit

Bit Insert Circuit

Transmit Latch

G0TCRC

Register

Data

Selector

Transmission

Transmit Interrupt Request

SIO0TR(1)

TXSL

0

1

G0TO Register

Transmit

Register

Transmit

Buffer

ISTxD0

HDLC Data Transmit

Interrupt Request

G0TOR(1)

G0RI Register

Receive

Buffer

Receive

Register

0

1

RXSL

Arbitration

G0DR Register

(Receive Data Register)

Shift

Register

Buffer

Register

G0CMP0 register

G0CMP0 register

G0CMP0 register

G0CMP3 Register

G0RCRC

Register

Receive Data

Generation Circuit

Bit Insert Check

Data

Selector

Comparator

Comparator

Comparator

Comparator

Reception

G0RB Register

Receive

Buffer

Receive

Register

Special Interrupt

Check

Receive Interrupt

Request

SIO0RR(1)

Special

Communication

Interrupt Request

SRT0R(1)

HDLC Data Receive

Interrupt Request

G0RIR(1)

f1

f2n

f8

ISCLK1

ISRxD1

Communication Unit 1

G1TB Register

(Transmit Buffer Register)

Transmit

Buffer

CCS3 and CCS2

01

10

11

0

1

CKDIR

Transmit

Operation

Clock

Receive

Operation

Clock

Transmit

Register

Clock Wait

Control Circuit

SOF

Generation Circuit

Transmit Data

Generation Circuit

Bit Insert Circuit

Transmit Latch

G1TCRC

Register

Data

Selector

Transmission

Transmit Interrupt

Request

SIO1TR(1)

TXSL 0 Polarity

Inverse

1

G1TO Register

Transmit

Register

Transmit

Buffer

ISTxD1

HDLC Data

Transmit

Interrupt Request

G1TOR(1)

G1RI Register

Receive

Buffer

Receive

Register

0

1

RXSL

NOTE:

1. See Figure 10.14.

Arbitration

G1DR Register

(Receive Data Register)

Shift

Register

Buffer

Register

G1CMP0 Register

G1C(8MbPit0) Register

G1C(M8bPit0) Register

G1C(8MbPit3) Register

G1RCRC

Register

Receive Data

Generation Circuit

Bit Insert Check

Data

Selector

Comparator

C(o8mbipt)arator

C(o8mbipt)arator

C(o8mbipt)arator

Reception

G1RB Register

Receive

Buffer

Receive

Register

Special Interrupt

Check

CKDIR: Bit in the GiMR Register (i=0,1)

TXSL, RXSL: Bits in the GiEMR Register

CCS1 and CCS0: Bits in the CCS Register

Receive Interrupt

Request

SIO1RR(1)

Special

Communication

Interrupt Request

SRT1R(1)

HDLC Data Receive

Interrupt Request

G1RIR(1)

Figure 21.1 Intelligent I/O Communication Unit Block Diagram

Rev. 1.00 Nov. 01, 2005 Page 245 of 330

REJ09B0271-0100

▷