M32C80 Datasheet, PDF (171/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer B)
Timer Bi Mode Register (i=0 to 5) (Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
Bit
Symbol
Bit Name
Function
RW
TMOD0 _{Operating Mode}
TMOD1 ^{Select Bit}
MR0
MR1
Count Polarity Select
Bit⁽¹⁾
b1b0
RW
0 1: Event counter mode
RW
b3b2
0 0: Counts falling edges of external signal _RW
0 1: Counts rising edges of external signal
1 0: Counts falling and rising edges of
external signal
RW
1 1: Do not set to this value
TB0MR and TB3MR registers:
Set to "0" in event counter mode
RW
MR2
TB1MR, TB2MR, TB4MR and TB5MR registers:
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
MR3
Disabled in event counter mode. When write, set to "0".
When read, its content is indeterminate.
TCK0
Disabled in event counter mode.
Can be set to "0" or "1".
RW
TCK1
Event Clock
Select Bit
0: Input signal from the TBiIN pin
1: TBj overflows or underflows⁽²⁾
RW
NOTES:
1. MR0 and MR1 bit settings are enabled when the TCK1 bit is set to "0". The MR1 bit can be set to
either "0" or "1", when the TCK1 bit is set to "1".
2. j=i-1, except j=2 when i=0 and j=5 when i=3.
Figure 14.21 TB0MR to TB5MR Registers
Rev. 1.00 Nov. 01, 2005 Page 152 of 330
REJ09B0271-0100