M32C80 Datasheet, PDF (237/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
Microcomputer
TxDi
RxDi
16. Serial I/O (Special Function)
SIM card
Figure 16.30 SIM Interface Connection
i=0 to 4
16.7.1 Parity Error Signal
16.7.1.1 Parity Error Signal Output Function
When the UiERE bit in the UiC1 register (i=0 to 4) is set to "1" (output), the parity error signal output
can be provided. The parity error signal output is provided when a parity error is detected upon
receiving data. A low-level ("L") signal output is provided from the TxDi pin in the timing shown in
Figure 16.31. When reading the UiRB register during a parity error output, the PER bit in the UiRB
register is set to "0" (no error occurs) and a high-level ("H") signal output is again provided simulta-
neously.
16.7.1.2 Parity Error Signal
To determine whether the parity error signal is output, the port that shares a pin with the RxDi pin is
read by using an end-of-transmit interrupt routine.
"H"
Transfer Clock
"L"
"H"
RxDi
"L"
"H"
TxDi
"L"
Recieve ^"1"
Complete Flag _"0"
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Hi-Z
NOTE:
1. The above applies to direct format.
(The PRY bit is set to "1", the UFORM bit is set to "0",
and the UiLCH bit is set to "0").
ST: Start bit
P: Even parity
SP: Stop bit
i=0 to 4
Figure 16.31 Parity Error Signal Output Timing (LSB First)
Rev. 1.00 Nov. 01, 2005 Page 218 of 330
REJ09B0271-0100