M32C80 Datasheet, PDF (220/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
Table 16.20 Register Settings in Special Mode 2
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
i=0 to 4
Bit
Function
7 to 0
Set transmit data
7 to 0
Received data can be read
OER
Overrun error flag
7 to 0
Set bit rate
SMD2 to SMD0 Set to "0012"
CKDIR
Set to "0" in master mode or "1" in slave mode
IOPOL
Set to "0"
CLK1, CLK0
Select count source for the UiBRG register
CRS
Disabled because the CRD bit is set to "1"
TXEPT
Transfer register empty flag
CRD
Set to "1"
NCH
Select the output format of the TxDi pin
CKPOL
Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in
the UiSMR3 register
UFORM
Select either LSB first or MSB first
TE
Set to "1" to enable data transmission and reception
TI
Transfer buffer empty flag
RE
Set to "1" to enable data reception
RI
Reception complete flag
UiIRS
Select what causes the UARTi transmit interrupt to be generated
UiRRM
Set to "1" to enable continuous receive mode
UiLCH, SCLKSTPB Set to "0"
7 to 0
Set to "0016"
7 to 0
Set to "0016"
SSE
Set to "1"
CKPH
Clock phase can be set by the combination of the CKPH bit and the CKPOL bit
in the UiC0 register
DINC
Set to "0" in master mode or "1" in slave mode
NODC
Set to "0"
ERR
Fault error flag
7 to 5
Set to "0002"
7 to 0
Set to "0016"
Rev. 1.00 Nov. 01, 2005 Page 201 of 330
REJ09B0271-0100