M32C80 Datasheet, PDF (149/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer A)
14.1 Timer A
Figure 14.3 shows a block diagram of the timer A. Figures 14.4 to 14.7 show registers associated with the
timer A.
The timer A supports the following four modes. Except in event counter mode, all timers A0 to A4 have the
same function. The TMOD1 and TMOD0 bits in the TAiMR register (i=0 to 4) determine which mode is
used.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts an external pulse or an overflow and underflow of other timers.
• One-shot timer mode: The timer outputs one valid pulse until a counter value reaches "000016".
• Pulse width modulation mode: The timer continuously outputs desired pulse widths.
Table 14.1 lists TAiOUT pin settings when used as an output. Table 14.2 lists TAiIN and TAiOUT pin settings
when used as an input.
Select clock
Select Count Source
TCK1 and
TCK0
f1 ⁰⁰
f8 ⁰¹
f2n^{(1) 10}
11
fC32
• Timer Mode
:TMOD1 and TMOD0=00, MR2=0
• One-Shot Timer Mode :TMOD1 and TMOD0=10
• Pulse Width Modulation Mode
:TMOD1 and TMOD0=11 ^{TMOD1 and TMOD0,}
MR2
• Timer Mode (gate function):
TMOD1 and TMOD0=00, MR2=1
• Event Counter Mode:TMOD1 and TMOD0=01
High-Order Bits of Data Bus
Low-Order Bits of Data Bus
8 low-
order
bits
Reload Register
8 high-
order
bits
Polarity
Selector
TAiIN
TB2 Overflow⁽²⁾
TAj Overflow⁽²⁾
TAk Overflow⁽²⁾
00
01
10
11
TAiTGH and TAiTGL
TAiS
TAiUD
Counter
Increment / decrement
Always decrement except
in event counter mode
00
01
11
Decrement
01
TMOD1 and TMOD0
0
1
TAiOUT
Pulse Output
MR2
Toggle Flip Flop
i=0 to 4
j=i-1, except j=4 if i=0
k=i+1, except k=0 if i=4
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select
no division (n=0) or divide-by-2n (n=1 to 15).
2. Overflow or underflow signal
TAi Addresses
TAj
TAk
Timer A0 034716 034616 Timer A4 Timer A1
Timer A1 034916 034816 Timer A0 Timer A2
Timer A2 034B16 034A16 Timer A1 Timer A3
Timer A3 034D16 034C16 Timer A2 Timer A4
Timer A4 034F16 034E16 Timer A3 Timer A0
TCK1 and TCK0, TMOD1 and TMOD0, MR2 and MR1: Bits in the TAiMR register
TAiTGH and TAiTGL: Bits in the ONSF register if i=0 or bits in the TRGSR register if i=1 to 4
TAiS: Bits in the TABSR register
TAiUD: Bits in the UDF register
Figure 14.3 Timer A Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 130 of 330
REJ09B0271-0100