M32C80 Datasheet, PDF (276/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
21. Intelligent I/O (Communication Function)
Table 21.4 Clock Settings (Communication Unit 1)
Transfer Clock
G1MR Register
CKDIR Bit
CCS Register
CCS2 Bit
CCS3 Bit
f8
0
1
1
f2n(2)
0
0
1
Input from ISCLK1
1
-
-
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Table 21.5 Register Settings in Clock Synchronous Serial I/O Mode
Register
CCS
GiERC
GiMR
GiCR
GiTB
GiRB
Bit
CCS1, CCS0
CCS3, CSS2
7 to 0
GMD1, GMD0
CKDIR
UFORM
IRS
TI
TXEPT
RI
TE
RE
–
–
Function
Communication Unit 1
Communication Unit 0
Setting not required when using the Select transfer clock
communication unit 1 only
Select transfer clock
Setting not required when using the
Set to "0010 00002"
communication unit 0 only
Set to "012"
Select internal clock or external clock
Select either LSB first or MSB first
Select what cause the transmit interrupt to be generated
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Set to "1" to enable transmission and reception
Set to "1" to enable reception
Write data to be transmitted
Received data and error flag are stored
i=0, 1
Table 21.6 Pin Settings in Clock Synchronous Serial I/O Mode (1)
Setting
Port
Function
PS1 Register PSL1 Register PSC Register
P73 ISTxD1 Output PS1_3=1
PSL1_3=0
PSC_3=1
P74 ISCLK1 Input PS1_4=0
-
-
ISCLK1 Output PS1_4=1
PSL1_4=0
PSC_4=1
PSD1 Register PD7 Register
-
-
-
PD7_4=0
-
-
P75 ISRxD1 Input PS1_5=0
P76 ISTxD0 Output PS1_6=1
P77 ISCLK0 Input PS1_7=0
ISCLK0 Output PS1_7=1
-
PSL1_6=0
-
PSL1_7=0
-
PSC_6=0
-
-
-
PSD1_6=0
-
-
PD7_5=0
-
PD7_7=0
-
Table 21.7 Pin Settings (2)
Setting
Port
Function
PS2 Register PD8 Register
P80 ISRxD0 Input PS2_0=0
PD8_0=0
Rev. 1.00 Nov. 01, 2005 ^{Page 257} of 330
REJ09B0271-0100