M32C80 Datasheet, PDF (52/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
5. Reset
5.2 Software Reset
Pins, the CPU and SFRs are reset when the PM03 bit in the PM0 register is set to "1" (microcomputer
reset). Then the microcomputer executes the program in an address determined by the reset vector.
Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is
stable.
In the software reset, the microcomputer does not reset a part of SFR. Refer to 4. Special Function
Registers (SFRs) for details. Processor mode remains unchanged since the PM01 and PM00 bits in the
PM0 register are not reset.
5.3 Watchdog Timer Reset
Pins, the CPU and SFRs are reset when the CM06 bit in the CM0 register is set to "1" (reset) and the
watchdog timer underflows. Then the microcomputer executes the program in an address determined by
the reset vector.
In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special
Function Registers (SFRs) for details. Processor mode remains unchanged since the PM01 and PM00
bits in the PM0 register are not reset.
5.4 Internal Space
Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR
states after reset.
0 : "0" after reset
X : Indeterminate after reset
General Registers
b15
b0
Flag Register (FLG)
b15
b8 b7
b0
X000XXXX00000000
IPL
b23
U I OB SZ DC
b0
0016
0016
Data Register (R0H/R0L)
0016
0016
Data Register (R1H/R1L)
000016
000016
00000016
Data Register (R2)
Data Register (R3)
Address Register (A0)
00000016
Address Register (A1)
00000016
Static Base Register (SB)
00000016
Frame Base Register (FB)
00000016
00000016
00000016
Contents of addresses
FFFFFE16 to FFFFFC16
User Stack Pointer (USP)
Interrupt Stack Pointer (ISP)
Interrupt Table Register (INTB)
Program Counter (PC)
High-speed Interrupt Registers
b15
b0
b23
XXXX16
Flag Save Register (SVF)
XXXXXX16
PC Save Register (SVP)
XXXXXX16
Vector Register (VCT)
DMAC-associated Registers
b7
b0
0016
DMA Mode Register (DMD0)
b15
0016
XXXX16
DMA Mode Register (DMD1)
DMA Transfer Count Register (DCT0)
XXXX16
DMA Transfer Count Register (DCT1)
XXXX16
DMA Transfer Count Reload Register (DRC0)
b23
XXXX16
XXXXXX16
DMA Transfer Count Reload Register (DRC1)
DMA Memory Address Register (DMA0)
XXXXXX16
DMA Memory Address Register (DMA1)
XXXXXX16
DMA Memory Address Reload Register (DRA0)
XXXXXX16
DMA Memory Address Reload Register (DRA1)
XXXXXX16
DMA SFR Address Register (DSA0)
XXXXXX16
DMA SFR Address Register (DSA1)
Figure 5.3 CPU Register States after Reset
Rev. 1.00 Nov. 01, 2005 Page 33 of 330
REJ09B0271-0100