M32C80 Datasheet, PDF (141/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
13. DMACII
13.1.2 DMAC II Index
The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple
transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter,
source address (or immediate data), operation address as an address to be calculated, destination ad-
dress, chained transfer address, and end-of-transfer interrupt address.
This DMAC II index must be located on the RAM area.
Figure 13.2 shows a configuration of the DMAC II index. Table 13.2 lists a configuration of the DMAC II
index in transfer mode.
Memory-to-Memory Transfer, Immediate Transfer,
Calculation Transfer
16 bits
DMAC II Index
Starting Address
(BASE)
BASE + 2
Transfer Mode
Transfer Counter
(MOD)
(COUNT)
BASE
BASE + 2
Multiple Transfer
16 bits
Transfer Mode
Transfer Counter
(MOD)
(COUNT)
BASE + 4
BASE + 6
Transfer Source Address (or immediate data) (SADR)
Operation Address⁽¹⁾
(OADR)
BASE + 4 Transfer Source Address
BASE + 6 Transfer Destination Address
(SADR1)
(DADR1)
BASE + 8
BASE + 10
BASE + 12
BASE + 14
BASE + 16
Transfer Destination Address
Chained Transfer Address⁽²⁾
Chained Transfer Address⁽²⁾
End-of-Transfer Interrupt Address⁽³⁾
End-of-Transfer Interrupt Address⁽³⁾
(DADR)
(CADR0)
(CADR1)
(IADR0)
(IADR1)
BASE + 8 Transfer Source Address
BASE + 10 Transfer Destination Address
BASE + 28 Transfer Source Address
BASE + 30 Transfer Destination Address
(SADR2)
(DADR2)
(SADR7)
(DADR7)
NOTES:
1. This data is not required when not using the calculation transfer function.
2. This data is not required when not using the chained transfer function.
3. This data is not required when not using the end-of-transfer interrupt.
The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation
transfer function, set destination address to BASE+6. (See Table 13.2)
Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request.
Figure 13.2 DMAC II Index
The followings are details of the DMAC II index. Set these parameters in the specified order listed in
Table 13.2, according to DMAC II transfer mode.
• Transfer mode (MOD)
Two-byte data is required to set transfer mode. Figure 13.3 shows a configuration for transfer mode.
• Transfer counter (COUNT)
Two-byte data is required to set the number of transfer.
• Transfer source address (SADR)
Two-byte data is required to set the source memory address or immediate data.
• Operation address (OADR)
Two-byte data is required to set a memory address to be calculated. Set this data only when using
the calculation transfer function.
• Transfer destination address (DADR)
Two-byte data is required to set the destination memory address.
• Chained transfer address (CADR)
Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set
this data only when using the chained transfer function.
• End-of-transfer interrupt address (IADR)
Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this
data only when using the end-of-transfer interrupt.
Rev. 1.00 Nov. 01, 2005 Page 122 of 330
REJ09B0271-0100