M32C80 Datasheet, PDF (223/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
16.4.2 Clock Phase Setting Function
The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four
combinations of transfer clock polarity and phases.
The transfer clock phase and polarity must be the same between the master and the slave involved in the
transfer.
16.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))
Figure 16.24 shows transmit and receive timing.
16.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))
_____
When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin
_____
is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a
serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the
transfer clock. Figure 16.25 shows the transmit and receive timing.
_____
When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high, the STxDi pin is placed
_____
in a high-impedance state. When the SSi pin becomes low, the first data is output. The serial transmis-
sion is synchronized with the transfer clock. Figure 16.26 shows the transmit and receive timing.
Signal Applied to
"H"
the SS Pin
"L"
Clock Output
"H"
(CKPOL=0, CKPH=0) _"L"
Clock Output
"H"
(CKPOL=1, CKPH=0) _"L"
Clock Output
"H"
(CKPOL=0, CKPH=1) _"L"
Clock Output
"H"
(CKPOL=1, CKPH=1) _"L"
Data Output Timing ^"H"
"L"
Data Input Timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 16.24 Transmit and Receive Timing in Master Mode (Internal Clock)
Rev. 1.00 Nov. 01, 2005 Page 204 of 330
REJ09B0271-0100