M32C80 Datasheet, PDF (271/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
21. Intelligent I/O (Communication Function)
SI/O Special Communication Interrupt Detect Register 0 ^{(1, 2)}
b7 b6 b5 b4 b3 b2 b1 b0
0 00
Symbol
G0IRF
Address
00FE16
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
Reserved Bit
Set to "0"
RW
(b1 - b0)
BSERR
Bit Stuffing Error
Detect Flag
0: Not detected
1: Detected
RW
Reserved Bit
Set to "0"
RW
(b3)
IRF0
Interrupt Source
Determination
Flag 0
0: The G0DR register (receive data register)
does not match the G0CMP0 register
1: The G0DR register matches the G0CMP0 ^RW
register
IRF1
Interrupt Source
Determination
Flag 1
0: The G0DR register (receive data register)
does not match the G0CMP1 register
1: The G0DR register matches the G0CMP1 ^RW
register
IRF2
IRF3
Interrupt Source
Determination
Flag 2
Interrupt Source
Determination
Flag 3
0: The G0DR register (receive data register)
does not match the G0CMP2 register
1: The G0DR register matches the G0CMP2
RW
register
0: The G0DR register (receive data register)
does not match the G0CMP3 register
1: The G0DR register matches the G0CMP3
RW
register
NOTES:
1. The G0IRF register is used in HDLC data processing mode. Do not use it in clock synchronous serial
I/O mode.
2. The SRT0R bit in the IIO4IR register is set to "1" if the IRF3 to IRF0 or BSERR bit is set to "1".
Figure 21.8 G0IRF Register
Rev. 1.00 Nov. 01, 2005 ^{Page 252} of 330
REJ09B0271-0100