M32C80 Datasheet, PDF (187/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O
RxDi
RxD Polarity
Switching Circuit
Clock Asynchronous
Selecting Clock Source
f1 ⁰⁰
f8 ⁰¹
f2n^{(2) 10}
CKDIR
0 ^Internal
CLK1 and 1
CLK0
External
UiBRG
Register
1 / (m+1)
Receive
SMD2 to SMD0
1/16 ^{010, 100, 101, 110}
001
Clock Synchronous
Receive
Control Circuit
Clock Asynchronous
Transmit
1/16 _{010, 100, 101, 110}
Clock Synchronous
001
Clock Synchronous (when
Transmit
Control Circuit
internal clock is selected)
1/2
0
1
CKPOL
CLK
Clock Synchronous
(when internal clock is selected)
Clock Synchronous
(when external clock
isCKDIR
selected)
CLKi
Polarity
Switching
CTSi / RTSi
Circuit
CTS/RTS
selected
1
CTS/RTS disabled
CRD
RTSi
Receive
Clock
Transmit
Clock
Transmit/
Receive
Unit
TxD
Polarity
Switching
Circuit
(Note 1)
RxDi
CRS 0
0 ^{CRD CTS/RTS disabled}
1
VSS
RxD Data
Inverse Circuit
IOPOL
No inverse
0
1
Inverse
CTSi
m: setting value of the UiBRG register
NOTES:
1. P70 and P71 are ports for the N-channel open drain output, but
not for the CMOS output.
2. The CNT3 to CNT0 bits in the TCSPR register select no division
(n=0) or divide-by-2n (n=1 to 15).
STPS
1SP
0
SP
SP
1
2SP
PRYE
PAR
Clock
disabled
0
Synchronous
PAR
1
Clock
PAR Asynchronous
enabled ^{SMD2 to SMD0}
Clock
Synchronous
7-bit Clock
Asynchronous
8-bit Clock
Asynchronous
0
7-bit Clock
Asynchronous
0
1
9-bit Clock
Asynchronous
Type
Clock 1
Synchronous
8-bit Clock
Asynchronous
9-bit Clock
Asynchronous
UARTi Receive Register
TxDi
0
0
0
0
0
0
0
D8
D8
D7
D6
D5
D4
D3
D2
D1
D0 _{UiRB Register}
Logic Inverse Circuit + MSB/LSB Conversion Circuit
High-order bits of data bus
Low-order bits of data bus
Logic Inverse Circuit + MSB/LSB Conversion Circuit
D7
D6
D5
D4
D3
D2
D1
D0
UiTB Register
8-bit Clock
Asynchronous
STPS
2SP
1
PRYE
PAR
enabled
1
SMD2 to SMD0
Clock
Asynchronous
1
9-bit Clock
Asynchronous
1
9-bit Clock
Asynchronous
Clock
Synchronous
1
SP
SP
PAR
0
1SP
0
Clock
PAR
Synchronous
disabled
0
0
7-bit Clock
Asynchronous
8-bit Clock
Asynchronous
Clock
Synchronous
0 _{7-bit Clock}
Asynchronous
UARTi Transmit Register
Error Signal Output
disable
0
IOPOL _{No inverse}
0
SP: Stop bit
PAR: Parity bit
i=0 to 4
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in the UiMR register
CLK1 and CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register
UiERE: Bit in the UiC1 register
Error Signal
UiERE 1 ^{Output Circuit}
Error Signal Output
enable
TxD Data
1 ^{Inverse Circuit}
Inverse
TxDi
Figure 16.1 UARTi Block Diagram
Rev. 1.00 Nov. 01, 2005 Page 168 of 330
REJ09B0271-0100