M32C80 Datasheet, PDF (178/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
15. Three-Phase Motor Control Timer Functions
Three-Phase PWM Control Register 0⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
INVC0
030816
After Reset
0016
Bit
Symbol
Bit Name
INV00
Interrupt Enable Output
Polarity Select Bit⁽³⁾
Function
RW
0: The ICTB2 counter is incremented by one on the
rising edge of the timer A1 reload control signal
1: The ICTB2 counter is incremented by one on the
RW
falling edge of the timer A1 reload control signal
INV01
Interrupt Enable Output
Specification Bit^{(2, 3)}
0: ICTB2 counter is incremented by one when
timer B2 counter underflows
RW
1: Selected by the INV00 bit
INV02 Mode Select Bit^{(4, 5, 6)}
0: Three-phase control timer function not used
1: Three-phase control timer function used
RW
INV03 ^{Output Control Bit(6, 7)}
0: Disables three-phase control timer output
1: Enables three-phase control timer output ^RW
Positive and Negative-
0: Enables concurrent active output
INV04
Phases Concurrent Active
Disable Function Enable Bit
1: Disables concurrent active output
RW
Positive and Negative-
0: Not detected
INV05 Phases Concurrent Active
Output Detect Flag⁽⁸⁾
1: Detected
RW
INV06
Modulation Mode
Select Bit^{(9, 10)}
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
RW
INV07
Software Trigger Select
Bit
Transfer trigger is generated when the
INV07 bit is set to "1". Trigger to the dead _RW
time timer is also generated when setting the
INV06 bit to "1". Its value is "0" when read.
NOTES:
1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
Rewrite the INV02 to INV00 and INV06 bits when the timers A1,A2, A4 and B2 stop.
2. Set the INV01 bit to "1" after setting the ICTB2 register.
3. The INV01 and INV00 bit settings are enabled only when the INV11 bit in the INVC1 register is set to "1"
(three-phase mode 1). The ICTB2 counter is incremented by one every time the timer B2 counter
underflows, regardless of INV01 and INV00bit settings, when the INV11 bit is set to "0" (three-phase mode).
When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 counter underflows.
When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1
times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the
timer B2 counter underflows.
4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2
counter.
5. Set pins after the INV02 bit is set to "1". See Table 16.2 for pin settings.
6. When the INV02 bit is set to "1" and the INV03 bit to "0", the U, U, V, V, W and W pins, including pins
shared with other output functions, are all placed in high-impedance states.
7. The INV03 bit is set to "0" when the followings occurs :
- Reset
- A concurrent active state occurs while the INV04 bit is set to "1"
- The INV03 bit is set to "0" by program
- An "H" signal applied to the NMI pin changes to an "L" signal
8. The INV05 bit can not be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit
to "0".
9. The following table describes how the INV06 bit setting works.
Item
INV06 = 0
INV06 = 1
Mode
Triangular wave modulation mode
Sawtooth wave modulation mode
Timing to Transfer from the IDB0 Transferred once by generating a
and IDB1 Registers to Three- transfer trigger after setting the IDB0
Phase Output Shift Register
and IDB1 registers
Transferred every time a transfer trigger
is generated
Timing to Trigger the Dead Time On the falling edge of a one-shot pulse By a transfer trigger, or the falling edge of
Timer when the INV16 Bit=0 of the timer A1, A2 or A4
a one-shot pulse of the timer A1, A2 or A4
INV13 Bit
Enabled when the INV11 bit=1 and the Disabled
INV06 bit=0
Transfer trigger: Timer B2 counter underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1
10. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the
TB2SC register to "0" (timer B2 counter underflows).
Figure 15.2 INVC0 Register
Rev. 1.00 Nov. 01, 2005 Page 159 of 330
REJ09B0271-0100