M32C80 Datasheet, PDF (114/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
Table 10.4 Interrupt Sequence Execution Time
Interrupt
Interrupt Vector Address
Peripheral Function
Even address
Odd address⁽¹⁾
INT Instruction
Even address
_______
NMI
Odd address⁽¹⁾
Even address⁽²⁾
Watchdog Timer
Undefined Instruction
Address Match
Overflow
Even address⁽²⁾
BRK Instruction (relocatable vector table) Even address
Odd address⁽¹⁾
BRK Instruction (fixed vector table)
Even address⁽²⁾
High-speed Interrupt
Vector table is internal register
NOTES:
1. Allocate interrupt vectors in even addresses.
2. Vectors are fixed to even addresses.
16-Bit Bus
14 cycles
16 cycles
12 cycles
14 cycles
13 cycles
14 cycles
17 cycles
19 cycles
19 cycles
5 cycles
8-Bit Bus
16 cycles
16 cycles
14 cycles
14 cycles
15 cycles
16 cycles
19 cycles
19 cycles
21 cycles
10.6.5 IPL Change when Interrupt Request is Acknowledged
When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowl-
edged interrupt.
Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has
no interrupt priority level is acknowledged, the value shown in Table 10.5 is set in IPL as the interrupt
priority level.
Table 10.5 Interrupts without Interrupt Priority Levels and IPL
Interrupt Source
_______
Watchdog Timer, NMI, Oscillation Stop Detection
Reset
Software, Address Match
Level Set to IPL
7
0
Not changed
Rev. 1.00 Nov. 01, 2005 Page 95 of 330
REJ09B0271-0100