M32C80 Datasheet, PDF (79/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
8. Clock Generation Circuit
Main Clock Division Register⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
MCD
Address
000C16
After Reset
XXX0 10002
Bit
Symbol
MCD0
MCD1
MCD2
MCD3
MCD4
Bit Name
Main Clock Division
Select Bit⁽²⁾
Function
RW
b4 b3 b2 b1 b0
1 0 0 1 0: Divide-by-1(no division) ^RW
mode
0 0 0 1 0: Divide-by-2 mode
0 0 0 1 1: Divide-by-3 mode
RW
0 0 1 0 0: Divide-by-4 mode
0 0 1 1 0: Divide-by-6 mode
RW
0 1 0 0 0: Divide-by-8 mode
0 1 0 1 0: Divide-by-10 mode
0 1 1 0 0: Divide-by-12 mode
RW
0 1 1 1 0: Divide-by-14 mode
0 0 0 0 0: Divide-by-16 mode
(Note 3) ^RW
Reserved Bit
(b7 - b5)
When read,
RO
its content is indeterminate
NOTES:
1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the microcomputer enters stop mode or low-power consumption mode, the MCD4 to MCD0 bits
are set to "010002".
The MCD4 to MCD0 bits are not set to "010002" even if the CM05 bit in the CM0 register is set to "1"
(XIN-XOUT stopped) in on-chip oscillator mode.
3. Bit combinations cannot be set not listed above.
Figure 8.4 MCD Register
Rev. 1.00 Nov. 01, 2005 Page 60 of 330
REJ09B0271-0100