M32C80 Datasheet, PDF (191/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O
UARTi Transmit/Receive Control Register 1 (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0C1 to U4C1
036D16, 02ED16, 033D16, 032D16, 02FD16
After Reset
0000 00102
Bit
Symbol
Bit Name
Function
RW
TE
Transmit
Enable Bit
0: Transmit disabled
1: Transmit enabled
RW
Transmit Buffer 0: Data in the UiTB register
TI _{Empty Flag}
1: No data in the UiTB register
RO
RE ^Receive
Enable Bit
0: Receive disabled
1: Receive enabled
RW
RI
Receive
0: No data in the UiRB register
Complete Flag 1: Data in the UiRB register
RO
UARTi Transmit _{0: No data in the UiTB register (TI = 1)}
UiIRS
Interrupt Cause
Select Bit
1: Transmission is completed (TXEPT = 1)
RW
UARTi
UiRRM
Continuous
Receive Mode
Enable Bit
0: Disables continuous receive mode to be entered
1: Enables continuous receive mode to be entered
RW
Data Logic
0: Not inversed
UiLCH _{Select Bit(2)}
1: Inverse
RW
Clock-Divided Clock-divided synchronous stop bit (special mode 3)
Synchronous Stop 0: Stops synchronizing
SCLKSTPB Bit /
/UiERE Error Signal
1: Starts synchronizing
Error signal output enable bit (special mode 5)
RW
Output Enable ^{0: Not output}
Bit⁽¹⁾
1: Output
NOTES:
1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register.
2. The UiLCH bit setting is enabled when setting the SMD2 to SMD0 bits to "0012" (clock syncronous
serial I/O mode), "1002" (UART mode, 7-bit transfer data) or "1012" (UART mode, 8-bit transfer data).
Set the UiLCH bit to "0" when setting the SMD2 to SMD0 bits to"0102" (I²C mode) or "1102" (UART
mode, 9-bit transfer data).
UARTi Special Mode Register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR to U4SMR
Address
036716, 02E716, 033716, 032716, 02F716
After Reset
0016
Bit
Symbol
Bit Name
IICM I²C Mode Select Bit
Function
0: Except I²C mode
1: I²C mode
Arbitration Lost Detect 0: Update per bit
ABC _{Flag Control Bit}
1: Update per byte
BBS Bus Busy Flag
0: Stop condition detected
1: Start condition detected (Busy)
SCLL Sync Output
LSYN _{Enable Bit}
0: Disabled
1: Enabled
ABSCS
Bus Conflict Detect
0: Rising edge of transfer clock
Sampling Clock Select Bit _{1: Timer Aj underflow(j=0 to 4)}(2)
Auto Clear Function Select 0: No auto clear function
ACSE _{Bit for Transmit Enable Bit 1: Auto clear at bus conflict}
SSS
Transmit Start
Condition Select Bit
0: Not related to RxDi
1: Synchronized with RxDi
Clock Divide
SCLKDIV _{Synchronous Bit}
(Note 3)
NOTES:
1. The BBS bit is set to "0" by program. It is unchanged if set to "1".
2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal,
UART2: timer A0 underflow signal, UART3: timer A3 underflow signal,
UART4: timer A4 underflow signal.
3. Refer to notes for the SU1HIM bit in the UiSMR2 register.
RW
RW
RW
RW⁽¹⁾
RW
RW
RW
RW
RW
Figure 16.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers
Rev. 1.00 Nov. 01, 2005 Page 172 of 330
REJ09B0271-0100