M32C80 Datasheet, PDF (116/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
10.6.8 Interrupt Priority
If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an
interrupt request is generated or not), the interrupt with the highest priority is acknowledged.
Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral function
interrupt).
Priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are
set by hardware. Figure 10.8 shows priority levels of hardware interrupts.
The interrupt priority does not affect software interrupts. Executing instruction causes the microcomputer
to execute an interrupt routine.
Reset
_______
> NMI
>
Oscillation Stop Detection
> Peripheral Function
> Address Match
Watchdog
Figure 10.8 Interrupt Priority
10.6.9 Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are sampled at the same sampling point.
Figure 10.9 shows the interrupt priority level select circuit.
Rev. 1.00 Nov. 01, 2005 Page 97 of 330
REJ09B0271-0100