M32C80 Datasheet, PDF (131/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
12. DMAC
Table 12.2 DMiSL Register (i=0 to 3) Function
Setting Value
DMA Request Source
b4 b3 b2 b1 b0
DMA0
DMA1
DMA2
DMA3
00000
00001
00010
Falling Edge of INT0
Both Edges of INT0
Software trigger
Falling Edge of INT1 Falling Edge of INT2
Both Edges of INT1 Both Edges of INT2
Falling Edge of INT3^{(1) (Note 2)}
Both Edges of INT3^{(1) (Note 2)}
00011
Timer A0 Interrupt Request
00100
Timer A1 Interrupt Request
00101
Timer A2 Interrupt Request
00110
Timer A3 Interrupt Request
00111
Timer A4 Interrupt Request
01000
Timer B0 Interrupt Request
01001
Timer B1 Interrupt Request
01010
Timer B2 Interrupt Request
01011
Timer B3 Interrupt Request
01100
Timer B4 Interrupt Request
01101
Timer B5 Interrupt Request
01110
01111
UART0 Transmit Interrupt Request
UART0 Receive or ACK Interrupt Request⁽³⁾
10000
10001
UART1 Transmit Interrupt Request
UART1 Receive or ACK Interrupt Request⁽³⁾
10010
10011
UART2 Transmit Interrupt Request
UART2 Receive or ACK Interrupt Request⁽³⁾
10100
10101
UART3 Transmit Interrupt Request
UART3 Receive or ACK Interrupt Request⁽³⁾
10110
10111
UART4 Transmit Interrupt Request
UART4 Receive or ACK Interrupt Request⁽³⁾
11000
11001
Intelligent I/O
Interrupt 0 Request
A/D0 Interrupt Request
Intelligent I/O
Interrupt 2 Request
11010
Intelligent I/O
Interrupt 1 Request
Intelligent I/O
Interrupt 3 Request
11011
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 4 Request
11100
11101
Intelligent I/O
Interrupt 3 Request
Intelligent I/O
Interrupt 4 Request
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 1 Request
11110
11111
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 1 Request
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 3 Request
NOTES:
1. If the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request
cannot be generated by a signal applied to the INT3 pin.
2. The falling edge and both edges of signals applied to the INTj pin (j=0 to 3) cause a DMA request generation. The
INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa.
3. Use the UkSMR register and UkSMR2 register (k=0 to 4) to switch between the UARTk receive and ACK interrupt
as a DMA request source.
To use the ACK interrupt for a DMA reqest, set the IICM bit in the UkSMR register to "1" and the IICM2 bit in the
UkSMR2 register to "0".
Rev. 1.00 Nov. 01, 2005 Page 112 of 330
REJ09B0271-0100