M32C80 Datasheet, PDF (241/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
17. A/D Converter
A/D0 Control Register 0⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AD0CON0
Address
039616
After Reset
0016
Bit
Symbol
Bit Name
Function
RW
b2 b1b0
CH0
0 0 0: AN0
RW
0 0 1: AN1
CH1
Analog Input Pin
Select Bit^{(2, 3, 6, 7)}
0 1 0: AN2
0 1 1: AN3
1 0 0: AN4
RW
1 0 1: AN5
CH2
1 1 0: AN6
RW
1 1 1: AN7
b4 b3
MD0
0 0: One-shot mode
RW
A/D Operating Mode _{0 1: Repeat mode}
Select Bit 0⁽²⁾
1 0: Single sweep mode
MD1
1 1: Repeat sweep mode 0 or 1
RW
TRG Trigger Select Bit
0: Software trigger
1: External trigger, hardware trigger^{(4) RW}
ADST
A/D Conversion
Start Flag
0: A/D conversion stops
1: A/D conversion starts⁽⁴⁾
RW
Frequency Select
CKS0 _Bit
(Note 5)
RW
NOTES:
1. When the AD0CON0 register is rewritten during the A/D conversion, the conversion result is
indeterminate.
2. Analog input pins must be set again after changing an A/D operating mode.
3. The CH2 to CH0 bit settings are enabled in one-shot mode and repeat mode.
4. To set the TRG bit to "1", select the cause of trigger by setting the TRG0 bit in the AD0CON2 register.
Then set the ADST bit to "1" after the TRG bit is set to "1".
5. AD frequency must be under 16 MHz when VCC1=5V.
AD frequency must be under 10 MHz when VCC1=3.3V.
Combination of the CKS0, CKS1 and CKS2 bits selects AD.
The CKS2 Bit in the
The CKS0 Bit in the
The CKS1 Bit in the
AD0CON3 Register
AD0CON0 Register
AD0CON1 Register
AD
0
0
fAD divided by 4
0
1
fAD divided by 3
1
0
fAD divided by 2
1
fAD
0
fAD divided by 8
1
0
1
fAD divided by 6
6. AVCC=VREF=VCC1, AD input voltage (for AN0 to AN7, ANEX0, ANEX1) ≤ VCC1.
7. Set the PSC_7 bit in the PSC register to "1" to use the P10 pin as an analog input pin.
Figure 17.2 AD0CON0 Register
Rev. 1.00 Nov. 01, 2005 ^{Page 222} of 330
REJ09B0271-0100