M32C80 Datasheet, PDF (212/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
Table 16.14 I²C Mode Functions
Function
Clock Synchronous
Serial I/O Mode
(SMD2 to SMD0=0012,
IICM=0)
I²C Mode (SMD2 to SMD0=0102, IICM=1)
IICM2=0
(NACK/ACK interrupt)
IICM2=1
(UART transmit / UART receive interrupt)
CKPH=0
CKPH=1
CKPH=0
CKPH=1
(No clock delay) (Clock delay) (No clock delay) (Clock delay)
Source for Interrupt
Numbers 39 to 41⁽¹⁾
-
(See Figure 16.20)
Start condition or stop condition detect (See Table 16.18)
Source for Interrupt
Number 17, 19, 33, 35
and 37⁽¹⁾
(See Figure 16.20)
UARTi Transmission -
Transmission started or
completed (selected by
the UiIRS register)
No Acknowledgement
Detection (NACK) -
Rising edge of 9th bit of SCLi
UARTi
Transmission -
Rising edge of
9th bit of SCLi
UARTi Transmission -
Next falling edge after the
9th bit of SCLi
Source for Interrupt
Numbers 18, 20, 34, 36
and 38⁽¹⁾
(See Figure 16.20)
UARTi Reception -
Receiving at 8th bit
CKPOL=0(rising edge)
CKPOL=1(falling edge)
Acknowledgement Detection
(ACK) -
Rising edge of 9th bit of SCLi
UARTi Reception -
Falling edge of 9th bit of SCLi
Data Transfer Timing from
the UART Receive Shift
Register to the UiRB Register
CKPOL=0(rising edge)
CKPOL=1(falling edge)
Rising edge of 9th bit of SCLi
Falling edge of Falling edge and rising edge
9th bit of SCLi of 9th bit of SCLi
UARTi Transmit Output
Delay
No delay
Delay
P63, P67, P70, P92, P96
Pin Functions
TxDi output
SDAi input and output
P62, P66, P71, P91, P97
Pin Functions
P61, P65, P72, P90, P95
Pin Functions
RxDi input
Select CLKi input or
output
SCLi input and output
– (Not used in I²C mode)
Noise Filter Width
15 ns
200 ns
Reading RxDi and SCLi
Pin Levels
Can be read if port
direction bit is set to "0"
Can be read regardless of the port direction bit
Default Value of TxDi,
SDAi Output
CKPOL=0 (H)
CKPOL=1 (L)
Values set in the port register before entering I²C mode⁽²⁾
SCLi Default and End
Value
–
H
L
H
L
Source for DMA
(See Figure 16.20)
UARTi reception
Acknowledgement detection
(ACK)
UARTi Reception -
Falling edge of 9th bit of SCLi
Store Received Data
1st to 8th bits of the
received data are stored
into bits 7 to 0 in the
UiRB register
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
1st to 7th bits of the received data are stored
into bits 6 to 0 in the UiRB register. 8th bit is
stored into bit 8 in the UiRB register.
1st to 8th bits are stored into
bits 7 to 0 in the UiRB
register⁽³⁾
Reading Received Data The UiRB register status is read
Bits 6 to 0 in the UiRB
registerts⁽⁴⁾ are read as bit 7
to 1. Bit 8 in the UiRB
register is read as bit 0
i=0 to 4
NOTES:
1. Use the following procedure to change what causes an interrupt to be generated.
(a) Disable interrupt of corresponding interrupt number.
(b) Change what causes an interrupt to be generated.
(c) Set the IR bit of a corresponding interrupt number to "0" (no interrupt requested).
(d) Set the ILVL2 to ILVL0 bits of a corresponding interrupt number.
2. Set default value of the SDAi output when the SMD2 to SMD0 bits in the UiMR register are set to "0002"
(serial I/O disabled).
3. Second data transfer to the UiRB register (on the rising edge of the ninth bit of SCLi).
4. First data transfer to the UiRB register (on the falling edge of the ninth bit of SCLi).
Rev. 1.00 Nov. 01, 2005 Page 193 of 330
REJ09B0271-0100