M32C80 Datasheet, PDF (102/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
10.2 Software Interrupts
Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable inter-
rupts.
10.2.1 Undefined Instruction Interrupt
The undefined instruction interrupt occurs when the UND instruction is executed.
10.2.2 Overflow Interrupt
The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic
operation) and the INTO instruction is executed.
Instructions to set the O flag are :
ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX
10.2.3 BRK Interrupt
The BRK interrupt occurs when the BRK instruction is executed.
10.2.4 BRK2 Interrupt
The BRK2 interrupt occurs when the BRK2 instruction is executed.
Do not use this interrupt. For development support tools only.
10.2.5 INT Instruction Interrupt
The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 8 to 48 are assigned to the vector table
used for the peripheral function interrupt. Therefore, the microcomputer executes the same interrupt rou-
tine when the INT instruction is executed as when a peripheral function interrupt occurs.
When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the
relocatable vector of specified software interrupt numbers. Where the stack is saved varies depending
on a software interrupt number. ISP is selected as the stack for software interrupt numbers 0 to 31
(setting the U flag to "0"). SP, which is set before the INT instruction is executed, is selected as the stack
for software interrupt numbers 32 to 63 (the U flag is not changed).
With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select)
when an interrupt request is acknowledged. With software interrupt numbers 32 to 48, SP to be used
varies depending on whether the interrupt is generated by the peripheral function interrupt request or by
the INT instruction.
Rev. 1.00 Nov. 01, 2005 Page 83 of 330
REJ09B0271-0100