M32C80 Datasheet, PDF (59/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
7. Bus
7.1.1 Selecting External Address Bus
The number of externally-output address buses, the number of chip-select signals and chip-select-as-
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signed address space (CS area) vary depending on each external space mode. The PM11 and PM10
bits in the PM1 register determine the external space mode.
7.1.2 Selecting External Data Bus
The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the
external space 3, after reset, becomes 16 bits wide when a low-level ("L") signal is applied to the BYTE
pin and 8 bits wide when a high-level ("H") signal is applied. Keep the BYTE pin input level while the
microcomputer is operating. Internal bus is always 16 bits wide.
7.1.3 Selecting Separate/Multiplexed Bus
The PM05 and PM04 bits in the PM0 register determine either separate or multiplexed bus as bus format.
7.1.3.1 Separate Bus
The separate bus is a bus format which allows the microcomputer to input and output data and ad-
dress separatelly. The DS register selects 8-bit or 16-bit data bus as the external data bus per exter-
nal space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P0 becomes the
data bus and port P1, the programmable I/O port. If one of the DSi bits is set to "1" (16-bit data bus),
ports P0 and P1 become the data bus. Port P1 is indeterminate when the microcomputer accesses a
space where the DSi bit is set to "0".
The EWCRi register (i=0 to 3) determines the number of software wait states inserted, when the
microcomputer accesses space using the separate bus.
7.1.3.2 Multiplexed Bus
The multiplexed bus is a bus format which allow the microcomputer to input and output data and
address by timesharing. D0 to D7 are multiplexed with A0 to A7 in space accessed by the 8-bit data
bus. D0 to D15 are multiplexed with A0 to A15 in space accessed by the 16-bit data bus. The DSi bit
controls the data bus width. The EWCRi register (i=0 to 3) controls the number of software wait states
inserted, when the microcomputer accesses a space using the multiplexed bus. Refer to 7.2.4 Bus
Timing for details.
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The multiplexed bus can be assigned to access the CS1 area, CS2 area or all CS areas. However,
because the microcomputer starts operation using the separate bus after reset, the multiplexed bus
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cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits
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in the PM0 register are set to "112" (access all CS areas with the bus), 16 low-order bits, from A0 to
A15, of an address are output. See Table 7.2 for details.
Rev. 1.00 Nov. 01, 2005 Page 40 of 330
REJ09B0271-0100