M32C80 Datasheet, PDF (342/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
24. Precautions (A/D Converter)
24.10 A/D Converter
• Set the AD0CON0 (bit 6 excluded), AD0CON1, AD0CON2, AD0CON3, and AD0CON4 registers while
the A/D conversion is stopped (before a trigger is generated).
• Wait a minimum of 1µs before starting the A/D conversion when changing the VCUT bit setting in the
AD0CON1 register from "0" (VREF no connection) to "1" (VREF connection).
Change the VCUT bit setting from "1" to "0" after the A/D conversion is completed.
• Insert capacitors between the AVCC pin, VREF pin, analog input pin ANi (i=0 to 7) and AVSS pin to
prevent latch-ups and malfunctions due to noise, and to minimize conversion errors. The same applies
to the VCC and VSS pins. Figure 24.4 shows the use of capacitors to reduce noise.
VCC1
C4
VCC2
C5
Microcomputer
VCC1
VCC
AVCC
VSS
VCC
VSS
VREF
C1
AVSS
ANi
C2
C3
ANi: ANi, AN0i, AN15i and AN2i (i=0 to 7)
NOTES:
1. C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 24.4 Use of Capacitors to Reduce Noise
• Set the bit in the port direction register, which corresponds to the pin being used as the analog input, to
__________
"0" (input mode). Set the bit in the port direction register, which corresponds to the ADTRG pin, to "0"
(input mode) if the TRG bit in the AD0CON0 register is set to "1" (external trigger).
• When generating a key input interrupt, do not use the AN4 to AN7 pins as analog input pins (key input
interrupt request is generated when the A/D input voltage becomes "L").
• The φAD frequency must be 16MHz or less. When the sample and hold function is not activated, the φAD
frequency must be 250 kHz or more. If the sample and hold function is activated, the φAD frequency
must be 1MHz or more.
• Set the CH2 to CH0 bits in the AD0CON0 register or the SCAN1 and SCAN0 bits in the AD0CON1
register to re-select analog input pins when changing A/D conversion mode.
Rev. 1.00 Nov. 01, 2005 ^{Page 323} of 330
REJ09B0271-0100