M32C80 Datasheet, PDF (7/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

10.2 Software Interrupts ................................................................................................ 83
10.2.1 Undefined Instruction Interrupt ..................................................................... 83
10.2.2 Overflow Interrupt ........................................................................................... 83
10.2.3 BRK Interrupt .................................................................................................. 83
10.2.4 BRK2 Interrupt ................................................................................................ 83
10.2.5 INT Instruction Interrupt ................................................................................. 83
10.3 Hardware Interrupts ............................................................................................... 84
10.3.1 Special Interrupts ............................................................................................ 84
10.3.2 Peripheral Function Interrupt ........................................................................ 84
10.4 High-Speed Interrupt ............................................................................................. 85
10.5 Interrupts and Interrupt Vectors ........................................................................... 85
10.5.1 Fixed Vector Tables ........................................................................................ 86
10.5.2 Relocatable Vector Tables .............................................................................. 86
10.6 Interrupt Request Acknowledgement ................................................................... 89
10.6.1 I Flag and IPL ................................................................................................... 89
10.6.2 Interrupt Control Register and RLVL Register ............................................. 89
10.6.3 Interrupt Sequence ......................................................................................... 93
10.6.4 Interrupt Response Time ................................................................................ 94
10.6.5 IPL Change when Interrupt Request is Acknowledged ............................... 95
10.6.6 Saving a Register ............................................................................................ 96
10.6.7 Restoration from Interrupt Routine ............................................................... 96
10.6.8 Interrupt Priority .............................................................................................. 97
10.6.9 Interrupt Priority Level Select Circuit ........................................................... 97
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10.7 INT Interrupt ............................................................................................................ 99
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10.8 NMI Interrupt ......................................................................................................... 100
10.9 Key Input Interrupt ............................................................................................... 100
10.10 Address Match Interrupt .................................................................................... 101
10.11 Intelligent I/O Interrupt ....................................................................................... 102
11. Watchdog Timer ____________________________ 105
11.1 Count Source Protection Mode ........................................................................... 108
12. DMAC_____________________________________ 109
12.1 Transfer Cycle ...................................................................................................... 116
12.1.1 Effect of Source and Destination Addresses ............................................. 116
12.1.2 Effect of the DS Register .............................................................................. 116
12.1.3 Effect of Software Wait State ....................................................................... 116
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12.1.4 Effect of RDY Signal ..................................................................................... 116
12.2 DMAC Transfer Cycle ........................................................................................... 118
12.3 Channel Priority and DMA Transfer Timing ....................................................... 118
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