M32C80 Datasheet, PDF (232/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
(1) The ABSCS Bit in the UiSMR Register (Bus conflict and sampling clock selected)
(i=0 to 4)
Bus conflict is detected on the rising edge of the transfer clock
when the ABSCS bit is set to "0"
Transfer Clock
TxDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RxDi
Trigger signal is applied to the TAjIN pin
Timer Aj
When the ABSCS bit is set to "1", bus conflict is detected when the timer Aj
underflows (in the one-shot timer mode). An interrupt request is generated.
Timer Aj: timer A3 in UART0 or UART3, timer A4 in UART1 or UART4, timer A0 in UART2
(2) The ACSE Bit in the UiSMR Register (Transmit enable bit is automatically cleared)
Transfer Clock
TxDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RxDi
IR bit in
BCNilC register
TE bit in
UiC1 register
(3) The SSS bit in the UiSMR Register (Transmit start condition is selected)
When the SSS bit is set to "0", data is transmitted after one transfer clock cycle
if data transmission is enabled.
Transfer Clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
CLKi
TxDi
RxDi
transmit enable conditons are met
When the SSS bit is set to "1", data is transmitted on the falling edge of RxDi⁽¹⁾
(Note 2)
ST D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
NOTES:
1. Data is transmitted on the falling edge of a signal applied to the RxDi pin when the IOPOL bit is set to "0".
Data is transmitted on the rising edge of a signal applied to the RxDi pin when the IOPOL bit is set to "1".
2. Data transmission condition must be met before the falling edge of the RxDi pin.
Figure 16.28 Bit Function Related Bus Conflict Detection
Rev. 1.00 Nov. 01, 2005 Page 213 of 330
REJ09B0271-0100