M32C80 Datasheet, PDF (73/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
7. Bus
(1) Separate Bus with 2 Wait States
1st cycle
2nd cycle
BCLK
3rd cycle
4th cycle
RD
(1)
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
(2) Multiplexed Bus with 2 Wait States
1st cycle
2nd cycle
BCLK
Timing to receive RDY
3rd cycle
4th cycle
RD
CSi ⁽¹⁾
(i=0 to 3)
RDY
tsu(RDY - BCLK)
: Wait states inserted by RDY
Timing to receive RDY
: Wait states inserted by program
tsu(RDY-BCLK): Setup time for RDY input
Timing to receive RDY for j wait(s): j+1 cycles (j = 1 to 3)
NOTE:
1. The chip-select signal (CSi) may be output longer depending on CPU state such as the instruction
queue buffer.
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Figure 7.11 RD Signal Output Extended by RDY Signal
Rev. 1.00 Nov. 01, 2005 Page 54 of 330
REJ09B0271-0100