M32C80 Datasheet, PDF (71/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
7. Bus
7.2.4.1 Bus Cycle with Recovery Cycle Added
The EWCRi06 bit in the EWCRi register (i=0 to 3) determines whether the recovery cycle is added or not.
In the recovery cycle, addresses and wrie data outputs are provided continuously (using the separate bus
only). Devices, which take longer address hold time and data hold time to write data, are connectable.
• Recovery Cycle with Separate Bus (For 1φ + 2φ)
Recovery Cycle
BCLK
Address
A
CSi ⁽¹⁾
<--- Hold an Address
Data (Read)
RD
RD
Data (Write)
WD
<--- Hold Data
WR, WRL, WRH
• Recovery Cycle with Multiplexed Bus (For 2φ + 3φ)
BCLK
CSi ⁽¹⁾
Data (Read)
LA
RD
Data (Write)
LA
WR (WRL)
ALE
RD
WD
Recovery Cycle
<--- Hold Data
A : Address LA : Latch Address RD : Read Data WD : Write Data
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area,
the CSi pin outputs an "L" signal continuously.
Figure 7.9 Recovery Cycle
Rev. 1.00 Nov. 01, 2005 Page 52 of 330
REJ09B0271-0100