M32C80 Datasheet, PDF (92/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
8. Clock Generation Circuit
Switch the CPU clock after the clock to be switched to stabilize. Sub clock oscillation will take longer⁽²⁾ to
stabilize. Wait, by program, until the clock stabilizes directly after turning the microcomputer on or exiting
stop mode.
To switch the on-chip oscillator clock to the main clock, enter medium-speed mode (divide-by-8) after the
main clock is divided by eight in on-chip oscillator mode (the MCD4 to MCD0 bits in the MCD register are
set to "010002").
Do not enter on-chip oscillator mode or on-chip oscillator low-power consumption mode from low-speed
mode or low-power consumption mode and vice versa.
NOTE:
2. Contact your oscillator manufacturer for oscillation stabilization time.
8.5.2 Wait Mode
In wait mode, the CPU clock stops running. The CPU and watchdog timer, operated by the CPU clock,
also stop. When the PM22 bit in the PM2 register is set to "1" (on-chip oscillator clock as watchdog timer
count source), the watchdog timer continues operating. Because the main clock, sub clock and on-chip
oscillator clock continue running, peripheral functions using these clocks also continue operating.
8.5.2.1 Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is set to "1" (peripheral function clock stops in wait mode), f1, f8, f32,
f2n (when peripheral clock is selected as a count source), and fAD stop in wait mode. Power consump-
tion can be reduced. f2n, when XIN clock or on-chip oscillator clock is selected as a count source, and
fC32 do not stop running.
8.5.2.2 Entering Wait Mode
If wait mode is entered after setting the CM02 bit to "1", set the MCD4 to MCD0 bits in the MCD
register to be the 10-MHz or less CPU clock flequency after dividing the main clock.
Enter wait mode after setting the followings.
• Initial Setting
Set each interrupt priority level after setting the exit priority level required to exit wait mode, con-
trolled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
• Before Entering Wait Mode
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit wait mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0"
(4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL
Interrupt priority level of the interrupt used to exit wait mode > IPL = the exit priority level
(5) Set the PRC0 bit in the PRCR register to "1"
(6) If the CPU clock source is the PLL clock, set the CM17 bit in the CM1 register to "0" (main clock)
and PLC07 bit in the PLC0 register to "0" (PLL off)
(7) Set the I flag to "1"
(8) Execute the WAIT instruction
• After Exiting Wait Mode
Set the exit priority level to "7" as soon as exiting wait mode.
Rev. 1.00 Nov. 01, 2005 Page 73 of 330
REJ09B0271-0100