M32C80 Datasheet, PDF (147/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer
14. Timer
The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each
timer functions independently. The count source for each timer becomes the clock for timer operations
including counting and reloading, etc. Figures 14.1 and 14.2 show block diagrams of timer A and timer B
configuration.
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
f1 f8 f2n fC32
Clock prescaler
XCIN
Set the CPSR bit in the
CPSRF register to "1"
1/32
Reset
TCK1 and TCK0
00
01
10
11
10
Noise 01
filter
00
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 and TMOD0
Timer A0
01: Event counter mode
11 TA0TGH and TA0TGL
TCK1 and TCK0
00
01
10
11
10
Noise 01
filter
00
00: Timer mode
10: One-shot tiemr mode
11: PWM mode
TMOD1 and TMOD0
Timer A1
01: Event counter mode
11 TA1TGH and TA1TGL
TCK1 and TCK0
00
01
10
11
Noise
filter
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 and TMOD0
10
Timer A2
01
00
01: Event counter mode
11 TA2TGH and TA2TGL
00TCK1 ^{and TCK0}
01
10
11
Noise
filter
00: Timer mode
10: One-shot timer mode
11: PWM mode
10
TMOD1 and TMOD0
Timer A3
01
00
01: Event counter mode
11 ^{TA3TGH and TA3TGL}
TCK1 and TCK0
00
01
10
11
10
Noise ⁰¹
filter
00
00: Timer mode
10: One-shot timer mode
11: PWM mode
TMOD1 and TMOD0
Timer A4
01: Event counter mode
11 TA4TGH and TA4TGL
fC32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer B2 overflow
or underflow signal
CST: Bit in the TCSPR Register
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TAiMR Register (i=0 to 4)
TAiTGH and TAiTGL: Bits in the ONSF Register or TRGSR Register
Figure 14.1 Timer A Configuration
Rev. 1.00 Nov. 01, 2005 Page 128 of 330
REJ09B0271-0100