M32C80 Datasheet, PDF (140/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
13. DMACII
Exit Priority Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RLVL
Address
009F16
After Reset
XXXX 00002
Bit
Symbol
Bit Name
Function
RW
RLVL0
b2b1b0
0 0 0: Level 0
RW
Stop/Wait Mode Exit
RLVL1 ^{Minimum Interrupt}
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
RW
Priority Level Control _{1 0 0: Level 4}
Bit⁽¹⁾
1 0 1: Level 5
RLVL2
1 1 0: Level 6
RW
1 1 1: Level 7
0: Interrupt priority level 7 is used
High-speed Interrupt
FSIT _{Set Bit}(2)
for normal interrupt
1: Interrupt priority level 7 is used
RW
for high-speed interrupt
Nothing is assigned. When write, set to "0".
(b4) ^{When read, its content is indeterminate.}
DMAII DMA II Select Bit⁽⁴⁾
0: Interrupt priority level 7 is used
for interrupt
RW
1: Interrupt priority level 7 is used
for DMA II transfer⁽³⁾
Nothing is assigned. When write, set to "0".
(b7 - b6) ^{When read, its content is indeterminate.}
NOTES:
1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than
the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in
the FLG register.
2. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed
interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0".
3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1".
Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0"
when the DMAII bit to "1".
4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it
to "0" before setting the interrupt control register.
Figure 13.1 RLVL Register
Rev. 1.00 Nov. 01, 2005 Page 121 of 330
REJ09B0271-0100