M32C80 Datasheet, PDF (236/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (Special Function)
(1) Transmit Timing
Tc
Transfer Clock
TE bit in the UiC1 ^"1"
register
"0"
TI bit in the UiC1 "1"
register
"0"
TxDi
Parity Error Signal
returned from
Receiving End
Signal Line Level⁽²⁾
TXEPT bit in the _"1"
UiC0 register
"0"
IR bit in the SiTIC "1"
register
"0"
Data is written to
the UiTB register
(Note 1)
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Data is transferred from the UiTB
register to the UARTi transmit
register
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An "L" signal is applied from the SIM
card due to a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
An interrupt routine
detects "H" or "L"
An interrupt routine detects
"H" or "L"
i=0 to 4
The above applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated
when transmission completed)
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16(m+1) / fj
fj: count source frequency of the UiBRG register (f1, f8, f2n(4))
m: setting value of the UiBRG register
(2) Receive Timing
Transfer Clock
RE bit in the UiC1 ^"1"
register
"0"
Transmit Waveform
from the
Transmitting End
TxDi
Signal Line Level⁽³⁾
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxDi outputs "L" due to
a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
RI bit in the UiC1 "1"
register
"0"
IR bit in the
"1"
SiRIC register
"0"
Read the UiRB register
i=0 to 4
The above applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16(m+1) / fj
fj: count source frequency of the UiBRG register (f1, f8, f2n(4))
m: setting value of the UiBRG register
NOTES:
1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit.
2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi
pin and parity error signal from the receiving end, is generated.
3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the
transmitting end and parity error signal from the TxDi pin, is generated.
4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15).
Figure 16.29 SIM Interface Operation
Rev. 1.00 Nov. 01, 2005 Page 217 of 330
REJ09B0271-0100