M32C80 Datasheet, PDF(142/352 Page) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

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M32C80 Datasheet, PDF (142/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

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M32C/80 Group

13. DMACII

Table 13.2 DMAC II Index Configuration in Transfer Mode

Transfer Data

Memory-to-Memory Transfer

/Immediate Data Transfer

Chained Transfer Not Used Used Not Used Used

Not Used

Calculation Transfer

Used Not Used

End-of-Transfer

Interrupt

Not Used

Not Used

Used

Used Not Used Not Used Used

Multiple Transfer

Used Not Available

Used Not Available

DMAC II

Index

MOD

COUNT

SADR

DADR

8 bytes

MOD

COUNT

SADR

DADR

CADR0

CADR1

MOD

COUNT

SADR

DADR

IADR0

IADR1

12 bytes 12 bytes

MOD

COUNT

SADR

DADR

CADR0

CADR1

IADR0

IADR1

16 bytes

MOD

COUNT

SADR

OADR

DADR

10 bytes

MOD

COUNT

SADR

OADR

DADR

CADR0

CADR1

14 bytes

MOD

COUNT

SADR

OADR

DADR

IADR0

IADR1

14 bytes

MOD

COUNT

SADR

OADR

DADR

CADR0

CADR1

IADR0

IADR1

18 bytes

MOD

COUNT

SADR1

DADR1

SADRi

DADRi

i=1 to 7

max. 32 bytes

(when i=7)

Transfer Mode (MOD)(1)

b15

b8 b7

b0

Bit

Symbol

Bit Name

SIZE Transfer Unit

Select Bit

Function

(MULT=0)

0: 8 bits

1: 16 bits

Function

(MULT=1)

RW

RW

Transfer Data

0: Immediate data

IMM Select Bit

1: Memory

Set to "1"

RW

UPDS Transfer Source 0: Fixed address

RW

Direction Select Bit 1: Forward address

Transfer Destination 0: Fixed address

UPDD Direction Select Bit 1: Forward address

RW

OPER/ Calculation Transfer 0: Not used

CNT0(2) Function Select Bit 1: Used

b6 b5 b4

0 0 0: Do not set RW

to this value

0 0 1: Once

BRST/ Burst Transfer

CNT1(2) Select Bit

0: Single transfer

1: Burst transfer

0 1 0: Twice

:

RW

:

INTE/ End-of-Transfer 0: Interrupt not used 1 1 0: 6 times

CNT2(2) Interrupt Select Bit 1: Use interrupt

1 1 1: 7 times

RW

CHAIN

Chained Transfer

Select Bit

0: Chained transfer not used Set to "0"

1: Use chained transfer

RW

Nothing is assigned. When write, set to "0".

(b14 - b8) When read, its content is indeterminate.

MULT Multiple Transfer

Select Bit

0: Multiple

transfer not used

1: Use multiple

transfer

RW

NOTES:

1. MOD must be located on the RAM.

2. When the MULT bit is set to "0" (no multiple transfer), bits 6 to 4 becomes the INTE, OPER and BRST

bits. When the MULT bit is set to "1" (multiple transfer), bits 6 to 4 becomes the CNT2 to CNT0 bits.

Figure 13.3 MOD

Rev. 1.00 Nov. 01, 2005 Page 123 of 330

REJ09B0271-0100

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