M32C80 Datasheet, PDF (143/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
13. DMACII
13.1.3 Interrupt Control Register for the Peripheral Function
For the peripheral function interrupt activating DMAC II, set the ILVL2 to ILVL0 bits to "1112" (level 7).
13.1.4 Relocatable Vector Table for the Peripheral Function
Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt
activating DMAC II.
When using the chained transfer, the relocatable vector table must be located in the RAM.
13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 4)
When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE
register of the interrupt to "0".
13.2 DMAC II Performance
Function to activate DMAC II is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II is
activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "1112" (level 7). These
peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral
function interrupt cannot be used.
When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "1112" (level 7), DMAC II is
activated regardless of what state the I flag and IPL are in.
13.3 Transfer Data
DMAC II transfers 8-bit or 16-bit data.
• Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space
(Addresses 0000016 to 0FFFF16) to another desired memory location in the same space.
• Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space.
• Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired
memory location in a 64-Kbyte space.
When a 16-bit data is transferred to the destination address 0FFFF16, it is transferred to 0FFFF16 and
1000016. The same transfer occurs when the source address is 0FFFF16. Actual transferable space varies
depending on the internal RAM capacity.
13.3.1 Memory-to-memory Transfer
Data transfer between any two memory locations can be:
• a transfer from a fixed address to another fixed address
• a transfer from a fixed address to a relocatable address
• a transfer from a relocatable address to a fixed address
• a transfer from a relocatable address to another relocatable address
When a relocatable address is selected, the address is incremented, after a transfer, for the next transfer.
In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer address is
incremented by two.
When a source or destination address exceeds address 0FFFF16 as a result of address incrementation,
the source or destination address returns to address 0000016 and continues incrementation. Maintain
source and destination address at address 0FFFF16 or below.
Rev. 1.00 Nov. 01, 2005 Page 124 of 330
REJ09B0271-0100