M32C80 Datasheet, PDF (169/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer B)
14.2.1 Timer Mode
In timer mode, the timer counts an internally generated count source (see Table 14.9). Figure 14.20
shows the TBiMR register (i=0 to 5) in timer mode.
Table 14.9 Timer Mode Specifications
Item
Specification
Count Source
f1, f8, f2n(1), fC32
Counting Operation
• The timer decrements a counter value
When the timer counter underflows, content of the reload register is reloaded into the
count register and counting resumes
Divide Ratio
1/(n+1) n: setting value of the TBi register (i=0 to 5) 000016 to FFFF16
Counter Start Condition
The TBiS bits in the TABSR and TBSR registers are set to "1" (starts counting)
Counter Stop Condition
The TBiS bit is set to "0" (stops counting)
Interrupt Request Generation Timing Timer counter underflows
TBiIN Pin Function
Programmable I/O port
Read from Timer
The TBi register indicates counter value
Write to Timer
• When the timer counter stops, the value written to the TBi register is also written to
both reload register and counter
• While counting, the value written to the TBi register is written to the reload register
NOTE:
(It is transferred to the counter at the next reload timing)
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Timer Bi Mode Register (i=0 to 5) (Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol
Address
After reset
TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002
Bit
Symbol
Bit Name
Function
RW
TMOD0
RW
Operating Mode
Select Bit
b1b0
0 0: Timer mode
TMOD1
RW
MR0 _{Disabled in timer mode.}
RW
MR1 ^{Can be set to "0" or "1".}
RW
TB0MR, TB3MR registers:
RW
Set to "0" in timer mode
MR2 _{TB1MR, TB2MR TB4MR, TB5MR registers:}
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
MR3 Set to "0" in timer mode
RW
b7 b6
TCK0
0 0: f1
RW
Count Source
0 1: f8
Select Bit
1 0: f2n(1)
TCK1
1 1: fC32
RW
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 14.20 TB0MR to TB5MR Registers
Rev. 1.00 Nov. 01, 2005 Page 150 of 330
REJ09B0271-0100