M32C80 Datasheet, PDF (110/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
10. Interrupts
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INT0IC to INT2IC
INT3IC to INT5IC⁽¹⁾
Address
009E16, 007E16, 009C16
007C16, 009A16, 007A16
After Reset
XX00 X0002
XX00 X0002
Bit
Symbol
Bit Name
Function
RW
b2b1b0
ILVL0
0 0 0: Level 0 (interrupt disabled) RW
0 0 1: Level 1
Interrupt Priority Level
ILVL1 _{Select Bit}
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
RW
1 0 1: Level 5
ILVL2
1 1 0: Level 6
1 1 1: Level 7
RW
IR Interrupt Request Bit
0: Requests no interrupt
1: Requests an interrupt⁽²⁾
RW
POL ^{Polarity Switch Bit}
0: Selects falling edge or "L"⁽³⁾
1: Selects rising edge or "H"
RW
Level Sensitive/Edge 0: Edge sensitive
LVS _{Sensitive Switch Bit}
1: Level sensitive⁽⁴⁾
RW
Nothing is assigned. When write, set to "0".
(b7 - b6) ^{When read, its content is indeterminate.}
NOTES:
1. When a 16-bit data bus is used in microprocessor or memory expansion mode, each INT3 to INT5
pin is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and INT5IC registers
to "0002".
2. The IR bit can be set to "0" only (do not set to "1").
3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges).
4. When setting the LVS bit to "1" , set a corresponding bit in the IFSR register to "0" (one edge).
Figure 10.4 Interrupt Control Register (2)
10.6.2.1 ILVL2 to ILVL0 Bits
The ILVL2 to ILVL0 bits determines an interrupt priority level. The higher the interrupt priority level is,
the higher interrupt priority is.
When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is
acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits
are set to "0002" (level 0), its interrupt is ignored.
10.6.2.2 IR Bit
The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The
IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and
an interrupt routine in the corresponding interrupt vector is executed.
The IR bit can be set to "0" by program. Do not set to "1".
Rev. 1.00 Nov. 01, 2005 Page 91 of 330
REJ09B0271-0100