M32C80 Datasheet, PDF (205/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (UART)
(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit)
The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin,
when the stop bit state is verified.
Tc ^{The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin}
Transfer Clock
TE bit in UiC1
"1"
register
"0"
TI bit in UiC1
"1"
register
"0"
"H"
CTSi
"L"
TxDi
TXEPT bit in UiC0 "1"
register
"0"
IR bit in SiTIC
"1"
register
"0"
Data is set in the UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
Start
bit
Parity
bit
Stop
bit
Pulse stops because the TE bit is set to "0"
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1
i=0 to 4
The above timing applies under the following conditions:
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The CRD bit in the UiC0 register is set to "0" and the CRS bit is set
to "0" (CTS function selected)
• The UilRS bit in the UiC1 register is set to "1"
(transmission completed)
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT
fj: count source frequency set in the UiBRG register (f1, f8, f2n(1))
fEXT: count source frequency set in the UiBRG register (external
clock)
m: setting value of the UiBRG register
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0)
or divide-by-2n (n=1 to 15).
(2) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
Tc
Transfer Clock
"1"
TE bit in UiC1
register
"0"
"1"
TI bit in UiC1
register
"0"
TxDi
TXEPT bit in UiC0 ^"1"
register
"0"
IR bit in SiTIC
"1"
register
"0"
Data is set in the UiTB register
Start
bit
Data is transferred from the UiTB register to the UARTi transmit register
Stop Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1
Set to "0" by an interrupt request acknowledgement or by program
i=0 to 4
The above timing applies under the following conditions:
• The PRYE bit in the UiMR register is set to "0" (parity disabled)
• The STPS bit in the UiMR register is set to "1" (2 stop bits)
• The CRD bit in the UiC0 register is set to "1" (CTS function
disabled)
• The UilRS bit in the UiC1 register is set to "0" (no data in the
transmit buffer)
Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT
fj: count source frequency set in the UiBRG register (f1, f8, f2n(1))
fEXT: count source frequency set in the UiBRG register (external
clock)
m: setting value of the UiBRG register
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division
(n=0) or divide-by-2n (n=1 to 15).
Figure 16.14 Transmit Operation
Rev. 1.00 Nov. 01, 2005 Page 186 of 330
REJ09B0271-0100