M32C80 Datasheet, PDF (137/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
12. DMAC
12.2 DMAC Transfer Cycle
The number of DMAC transfer cycle can be calculated as follows.
Any combination of even or odd transfer read and write addresses are possible. Table 12.3 lists the number
of DMAC transfer cycles. Table 12.4 lists coefficient j, k.
Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k
Table 12.3 DMAC Transfer Cycles
Transfer Unit
Bus Width Access Address
8-bit transfers
(BWi bit in the DMDp
register = 0)
16-bit transfers
(BWi bit = 1)
16-bit
8-bit
16-bit
8-bit
i= 0 to 3, p = 0, 1
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Single-Chip Mode
Read
Cycle
1
1
—
—
1
2
—
—
Write
Cycle
1
1
—
—
1
2
—
—
Memory Expansion Mode
Microprocessor Mode
Read
Write
Cycle
Cycle
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
Table 12.4 Coefficient j, k
Internal Space
Internal RAM Internal RAM SFR
with no wait state with a wait state area
j=1
j=2
j=2
k=1
k=2
k=2
j, k=2 to 9
External Space
j and k BCLK cycles shown in Table 7.5.
Add one cycle to j or k cycles when inserting a recovery cycle.
12.3 Channel Priority and DMA Transfer Timing
When multiple DMA requests are generated in the same sampling period, between the falling edge of the
CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i=0 to 3) is set to "1" (requested)
simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3.
Figure 12.7 shows an example of the DMA transfer by external source.
In Figure 12.7, the DMA0 request having highest priority is received first to start a transfer when a DMA0
request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts.
After one DMA1 transfer is completed, the privilege is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when
DMA requests, as DMA1 in Figure 12.7, occur more than once before receiving bus privilege, the DRQ bit
is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is
completed.
Rev. 1.00 Nov. 01, 2005 Page 118 of 330
REJ09B0271-0100