M32C80 Datasheet, PDF (179/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
15. Three-Phase Motor Control Timer Functions
Three-Phase PWM Control Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INVC1
Address
030916
After Reset
0016
Bit
Symbol
Bit Name
Timer A1, A2 and A4
INV10 _{Start Trigger Select Bit}
Timer A1-1, A2-1 and
INV11 _{A4-1 Control Bit(2, 3)}
Function
RW
0: Timer B2 counter underflows
1: Timer B2 counter underflows and RW
write to the TB2 register
0: Three-phase mode 0
1: Three-phase mode 1
RW
Dead Time Timer
0: f1
INV12 _{Count Source Select Bit 1: f1 divided-by-2}
RW
INV13
Carrier Wave Detect Flag⁽⁴⁾
0: Timer A1 reload control signal is "0"
1: Timer A1 reload control signal is "1"
RO
0: High active of an output waveform
INV14 Output Polarity Control Bit _{1: Low active of an output waveform} RW
INV15 ^{Dead Time Disable Bit}
0: Enables dead time
1: Disables dead time
RW
INV16
0: Falling edge of a one-shot pulse of
Dead Time Timer Trigger
Select Bit
the timer A1, A2 and A4⁽⁵⁾
1: Rising edge of the three-phase output
RW
shift register (U-, V-, W-phase)
Reserved Bit
Set to "0"
RW
(b7)
NOTES:
1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
The timers A1, A2, A4, and B2 must be stopped during rewrite.
2. The following table lists how the INV11 bit setting works.
Item
INV11 = 0
INV11 = 1
Mode
Three-phase mode 0
Three-phase mode 1
TA11, TA21 and TA41 Registers Not used
Used
INV01 and INV00 Bit
in the INVC0 Register
Disabled. The ICTB2 counter is
incremented whenever the timer B2 _Enabled
counter underflows
INV13 Bit
Disabled
Enabled when INV11=1 and INV06=0
3. When the INV06 bit in the INVC0 registser is set to "1" (sawtooth wave modulation mode), set the
INV11 bit to "0". Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to
"0" (Timer B2 counter underflows).
4. The INV13 bit setting is enabled only when the INV06 bit is set to "0" (Triangular wave modulation
mode) and the INV11 bit to "1".
5. If the following conditions are all met, set the INV16 bit to "1":
• The INV15 bit is set to "0"
• The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit in
the INVC0 register is set to "1". (The positive-phase and negative-phase outputs always provide
opposite level signals.)
If the above conditions are not met, set the INV16 bit to "0".
Figure 15.3 INVC1 Register
Rev. 1.00 Nov. 01, 2005 Page 160 of 330
REJ09B0271-0100