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M32C80 Datasheet, PDF (322/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
M32C/80 Group
23. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
[Read Timing] (1φ + 1φ Bus Cycles)
BCLK
CSi
ADi
BHE
RD
DB
td(BCLK-CS)
18ns.max(1)
tcyc
td(BCLK-AD)
18ns.max(1)
td(BCLK-RD)
18ns.max
tac1(RD-DB)(2)
tac1(AD-DB)(2)
Hi-Z
tsu(DB-BCLK)
30ns.min(1)
th(BCLK-CS)
0ns.min
th(RD-CS)
0ns.min
th(BCLK-AD)
0ns.min
th(RD-AD)
0ns.min
th(BCLK-RD)
-3ns.min
th(RD-DB)
0ns.min
Vcc1=Vcc2=3.3V
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency.
tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2) + 1)
tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n = a + b)
[Write Timing] (1φ + 1φ Bus Cycles)
BCLK
CSi
ADi
BHE
WR,WRL,
WRH
DBi
td(BCLK-CS)
18ns.max
tcyc
td(BCLK-AD)
18ns.max
th(BCLK-CS)
0ns.min
th(WR-CS)(3)
th(BCLK-AD)
0ns.min
td(BCLK-WR) tw(WR)(3)
18ns.max
td(DB-WR)(3)
th(WR-AD)(3)
th(BCLK-WR)
0ns.min
th(WR-DB)(3)
NOTE:
3. Varies with operation frequency.
td(DB-WR)=(tcyc x m-20)ns.min
(if external bus cycle is aφ + bφ, m=b)
th(WR-DB)=(tcyc/2-20)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(if external bus cycle is aφ + bφ, n=(bx2)-1)
Measurement Conditions
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
tcyc=
109
f(BCLK)
Figure 23.6 VCC1=VCC2=3.3V Timing Diagram (1)
Rev. 1.00 Nov. 01, 2005 Page 303 of 330
REJ09B0271-0100