M32C80 Datasheet, PDF (145/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
13. DMACII
13.6 Chained Transfer
The CHAIN bit in MOD selects the chained transfer.
The following process initiates the chained transfer.
(1) Transfer, caused by a transfer request source, occurs according to the content of the DMAC II index.
The vectors of the request source indicates where the DMAC II index is allocated. For each request, the
BRST bit selects either single or burst transfer.
(2) When COUNT reaches "0", the contents of CADR1 and CADR0 are written to the vector of the request
source. When the INTE bit in MOD is set to "1", the end-of-transfer interrupt is generated simulta-
neously.
(3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the
DMAC II index indicated by the peripheral function interrupt vector rewritten in (2).
Figure 13.4 shows the relocatable vector and DMACII index when the chained transfer is in progress.
For the chained transfer, the relocatable vector table must be located in the RAM.
Relocatable Vector
INTB
RAM
DMAC II
Index(1)
BASE(1)
(CADR1 and
CADR0)
BASE(2)
DMAC II
Index(2)
BASE(2)
(CADR1 and
CADR0)
BASE(3)
Peripheral I/O interrupt vector causing DMAC II request
Default value of DMAC II is BASE(1).
The above vector is rewritten to BASE(2)
when a transfer is completed.
Starts at BASE(2) when next request conditions
are met.
Transferred according to the DMAC II Index.
The above vector is rewritten to BASE(3)
when a transfer is completed.
Figure 13.4 Relocatable Vector and DMAC II Index
13.7 End-of-Transfer Interrupt
The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer
interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt is generated when COUNT reaches "0."
Rev. 1.00 Nov. 01, 2005 Page 126 of 330
REJ09B0271-0100