M32C80 Datasheet, PDF (70/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
• Bus Cycle 3φ + 3φ
BCLK
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR (WRL)
ALE
1 bus cycle = 6φ
LA
RD
LA
WD
• Bus Cycle 3φ + 4φ
BCLK
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR (WRL)
ALE
1 bus cycle = 7φ
LA
RD
LA
WD
• Bus Cycle 3φ + 5φ
1 bus cycle = 8φ
BCLK
CSi ⁽¹⁾
Data (Read)
LA
RD
RD
Data (Write)
LA
WD
WR (WRL)
ALE
• Bus Cycle 3φ + 6φ
1 bus cycle = 9φ
BCLK
CSi ⁽¹⁾
Data (Read)
LA
RD
RD
Data (Write)
LA
WD
WR (WRL)
ALE
LA : Latch Address
RD : Read Data
WD : Write Data
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area,
the CSi pin outputs an "L" signal continuously.
Figure 7.8 Bus Cycle with Multiplexed Bus (2)
Rev. 1.00 Nov. 01, 2005 Page 51 of 330
REJ09B0271-0100
7. Bus