M32C80 Datasheet, PDF (66/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
• Bus Cycle 1φ + 1φ
1 bus cycle = 2φ
BCLK
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
• Bus Cycle 1φ + 2φ
BCLK
1 bus cycle = 3φ
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
• Bus Cycle 1φ + 3φ
BCLK
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
1 bus cycle = 4φ
• Bus Cycle 1φ + 4φ
BCLK
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
1 bus cycle = 5φ
• Bus Cycle 1φ + 5φ
BCLK
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
1 bus cycle = 6φ
• Bus Cycle 1φ + 6φ
BCLK
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
1 bus cycle = 7φ
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area, the CSi pin outputs an "L" signal continuously.
Figure 7.4 Bus Cycle with Separate Bus (1)
7. Bus
Rev. 1.00 Nov. 01, 2005 Page 47 of 330
REJ09B0271-0100