M32C80 Datasheet, PDF (77/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
8. Clock Generation Circuit
System Clock Control Register 0⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
After Reset
0000 10002
Bit
Symbol
Bit Name
Function
RW
CM00
CM01
Clock Output Function
Select Bit⁽²⁾
b1 b0
0 0: I/O port P53
0 1: Outputs fC
1 0: Outputs f8
1 1: Outputs f32
RW
RW
0: Peripheral clock does not stop in
CM02
In Wait Mode, Peripheral
wait mode
Function Clock Stop Bit⁽⁹⁾ _{1: Peripheral clock stops in wait}
RW
mode⁽³⁾
CM03
XCIN-XCOUT Drive
Capacity Select Bit⁽¹¹⁾
0: Low
1: High
RW
CM04 Port XC Switch Bit
0: I/O port function
1: XCIN-XCOUT oscillation function⁽⁴⁾
RW
Main Clock (XIN-XOUT)
CM05 _{Stop Bit(5, 9)}
0: Main clock oscillates
1: Main clock stops⁽⁶⁾
RW
CM06 ^{Watchdog Timer}
Function Select Bit
0: Watchdog timer interrupt
1: Reset⁽⁷⁾
RW
CPU Clock Select
CM07 _{Bit 0(8, 9, 10)}
0: Clock selected by the CM21 bit
divided by MCD register setting
RW
1: Sub clock
NOTES:
1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 and CM00 bits to
"002". When the PM15 and PM14 bits in the PM1 register are set to "012" (ALE output to P53), set the
CM01 and CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 and
CM00 bits) in microprocessor or memory expansion mode, and the CM01 and CM00 bits are set to
"002", an "L" signal is output from port P53 (port P53 does not function as an I/O port).
3. fc32 does not stop running. When the CM02 bit is set to "1", the PLL clock cannot be used in wait
mode.
4. When setting the CM04 bit is set to "1", set the PD8_7 and PD8_6 bits in the PD8 register to "002"
(port P87 and P86 in input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up).
5. When entering low-power consumption mode or on-chip oscillator low-power consumption mode, the
CM05 bit stops running the main clock. The CM05 bit cannot detect whether the main clock stops or
not. To stop running the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable
sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock).
When the CM05 bit is set to "1", the clock applied to XOUT becomes "H". The built-in feedback resistor
remains ON. XIN is pulled up to XOUT ("H" level) via the feedback resistor.
6. When the CM05 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002"
(divide-by-8 mode). In on-chip oscillation mode, the MCD4 to MCD0 bits are not set to "010002" even
if the CM05 bit terminates XIN-XOUT.
7. Once the CM06 bit is set to "1", it cannot be set to "0" by program.
8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0".
After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1".
Do not set the CM07 bit and CM04 or CM05 bit simultaneously.
9. When the PM21 bit in the PM2 register is set to "1" (clock change disabled), the CM02, CM05 and
CM07 bits do not change even when written.
10. After the CM07 bit is set to "0", set the PM21 bit to "1".
11. When stop mode is entered, the CM03 bit is set to "1".
Figure 8.2 CM0 Register
Rev. 1.00 Nov. 01, 2005 Page 58 of 330
REJ09B0271-0100