M32C80 Datasheet, PDF (180/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
15. Three-Phase Motor Control Timer Functions
Three-Phase Output Buffer Register i⁽¹⁾ (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB0, IDB1
Address
030A16, 030B16
After Reset
XX11 11112
Bit
Symbol
Bit Name
Function
RW
DUi U-Phase Output Buffer i Write output level
RW
DUBi U-Phase Output Buffer i ^{0: Active level}
RW
1: Inactive level
DVi V-Phase Output Buffer i
RW
DVBi V-Phase Output Buffer i When read, the value of the three- RW
DWi W-Phase Output Buffer i ^{phase shift register is read.}
RW
DWBi W-Phase Output Buffer i
RW
Reserved Bit
(b7 - b6)
When read,
its content is indeterminate
RO
NOTE:
1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a
transfer trigger.
After the transfer trigger occurs, the values written in the IDB0 register determine each phase output
signal level first. Then the value written in the IDB1 register on the falling edge of the timers A1, A2
and A4 one-shot pulse determines each phase output signal level.
Dead Time Timer^{(1, 2)}
b7
b0
Symbol
DTT
Address
030C16
After Reset
Indeterminate
Function
Setting Range RW
If setting value is n, the timer stops when counting
n times a count source selected by the INV12 bit
after start trigger occurs. Positive or negative
1 to 255
WO
phase, which changes from inactive level to active
level, shifts when the dead time timer stops.
NOTES:
1. Use the MOV instruction to set the DTT register.
2. The DTT register setting is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time
enabled). No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06
bit in the INVC0 register determines start trigger of the DTT register.
Figure 15.4 IDB0 and IDB1 registers, DTT Register
Rev. 1.00 Nov. 01, 2005 Page 161 of 330
REJ09B0271-0100