M32C80 Datasheet, PDF (127/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
11. Watchdog Timer
11.1 Count Source Protection Mode
In count source protection mode, the on-chip oscillator clock is used as a count source for the watchdog
timer. The count source protection mode allows the on-chip oscillator clock to run continuously, maintain-
ing watchdog timer operation even if the program error occurs and the CPU clock stops running.
Follow the procedures below when using this mode.
(1) Set the PRC0 bit in the PRCR register to "1" (write to CM0 register enabled)
(2) Set the PRC1 bit in the PRCR register to "1" (write to PM2 register enabled)
(3) Set the CM06 bit in the CM0 register to "1" (reset when the watchdog timer overflows)
(4) Set the PM22 bit in the PM2 register to "1" (the on-chip oscillator clock as a count source of the watch-
dog timer)
(5) Set the PRC0 bit to "0" (write to CM0 register disabled)
(6) Set the PRC1 bit to "0" (write to PM2 register disabled)
(7) Write to the WDTS register (the watchdog timer starts counting)
The followings will occur when the PM22 bit is set to "1".
• The on-chip oscillator starts oscillating and the on-chip oscillator clock becomes a count source for
the watchdog timer.
Watchdog timer cycle =
Counter value of watchdog timer (32768)
On-chip oscillator clock
• Write to the CM10 bit in the CM1 register is disabled. (The bit setting remains unchanged even if set
it to "1". The microcomputer does not enter stop mode.)
• In wait mode or hold state, the watchdog timer continues running. However, the watchdog timer
interrupt cannot be used to exit wait mode.
Rev. 1.00 Nov. 01, 2005 Page 108 of 330
REJ09B0271-0100