M32C80 Datasheet, PDF (67/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
7. Bus
• Bus Cycle 2φ + 2φ
BCLK
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
1 bus cycle = 4φ
• Bus Cycle 2φ + 3φ
BCLK
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
1 bus cycle = 5φ
• Bus Cycle 2φ + 4φ
BCLK
Address
CSi ⁽¹⁾
Data (Read)
RD
Data (Write)
WR, WRL, WRH
1 bus cycle = 6φ
i=0 to 3
NOTE:
1. When the microcomputer continuously accesses the same CS area, the CSi pin outputs an "L" signal continuously.
Figure 7.5 Bus Cycle with Separate Bus (2)
Rev. 1.00 Nov. 01, 2005 Page 48 of 330
REJ09B0271-0100